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 코드번호 : 4 |
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| 발표자 : 김창훈 |
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| 소속 : Barefoot Networks / P4.org |
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| 부서 : |
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| 직위 : Executive Director |
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| 세션시간 : 09:00~11:00 |
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| 발표자약력 : |
Chang (Changhoon) Kim is Director of System Architecture at Barefoot Networks and is a chair of the Language-Design Working Group at the P4 Language Consortium (P4.org). Before getting involved with P4.org and Barefoot, he worked at Windows Azure, Microsoft’s cloud-service division, and led engineering and research projects on the architecture, performance, and management of datacenter networks. Chang is interested in programmable network data plane, network monitoring and diagnostics, network verification, self-programming/configuring networks, and debugging and diagnosis of large-scale distributed systems. Chang received Ph.D. from Princeton University. Many of his research contributions — including VL2, Seawall, EyeQ, Ananta, and SEATTLE — are adopted in large production networks. He is the recipient of Microsoft Rockstar Award 2013, an annual recognition for the strongest individual networking contributions Microsoft-wide. |
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| 강연요약 : |
Software-Defined Networking (SDN) has been successful because it lets network owners and operators “program” network behavior. SDN’s programmability, however, is confined to the network control plane today. The forwarding plane is still largely dictated by fixed-function packet-processing hardware. Our goal is to change that, and to allow programmers to define how packets are to be processed all the way down to the wire.
This is made possible by a new generation of high-performance forwarding chips. At the high-end, switching chips build with a new machine architecture -- namely PISA (Protocol-Independent Switch Architecture) -- promise multi-Tb/s of packet processing. At the mid- and low-end of the performance spectrum, CPUs, GPUs, FPGAs, and NPUs already offer great flexibility with performance of a few tens to hundreds of Gb/s. In addition to programmable forwarding chips, we also need a high-level language to dictate the forwarding behavior in a target independent fashion. "P4" (www.p4.org) is such a language. In P4, the programmer declares how packets are to be processed, and a compiler generates a configuration for a PISA chip, or a programmable target in general.
In this talk, I will first give a quick overview of PISA and explain why it is inevitable; within the next couple of years I expect all switching chips to be programmable, with no performance, power or cost penalty. I will then give a brief primer on the P4 language, showing some example programs for a variety of different networks, demonstrating the power of writing portable and reusable P4 programs. Finally I will introduce a few exciting use cases that data-plane programmability can enable, along with new challenges and problems warranting further study. |
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